[eresi-dev] JEDBG: new project in ERESI ?

[jfv]

Hello all,

Tomorrow, Julio Auto and I will meet Forger, a brazilian friend of us
who is up to start his end-of-bachelor project with us!

We have proposed him to do a JTAG debugger.

What is JTAG?

Those who deal with embedded systems might know already,
but for the others, JTAG is a a protocol for hardware-assisted
debugging of embedded software.

http://en.wikipedia.org/wiki/JTAG

If confirmed, this project will bring us to debugging embedded
systems. Our test environment will certainly be a ARM7-based
LPC-E2124 board such as this one:

http://www.olimex.com/dev/lpc-e2124.html

In other words, we have good chances that from March to July
2009, a new ERESI Team member will be dedicated to porting
ERESI for such debugging targets.

This works is a natural follow-up after our recent kernel debugger
(KEDBG) realized by Eric Bisolfati as an EPFL master project.

After being the first to provide graphs of kernel codes, may we
become the firsts to provide graphs of embedded codes ? ;)

If you are interested in this project, want to help or contribute
ideas, feel free to let us know. The exact requirement document
is not yet written and we will welcome any interesting suggestions.

-JFV / ERESI team